The present invention pertains to digital communication switching systems and more particularly to a data validity checking arrangement for the space switching stage of a time division multiplexing switching system.
In PCM communication switching systems, data, such as speakers' voices, is represented digitally. That is, speech samples are represented by a group of bits. Loss of any of these bits can significantly affect the voice sample. As a result, a method for ensuring the integrity of transmitted data is required.
Parity schemes may be utilized to detect and maintain data integrity. By using a parity scheme, it can be determined whether bits have become lost during transmission or whether bits are stuck at a particular logic 0 or logic 1 value. Two types of parity schemes exist, odd and even. In an odd parity scheme, the value of the parity bit would be a logic 1 if an even number of data bits have a value of logic 1. The value of the parity bit would be logic 0 if the value of an odd number of data bits have the value logic 1. In an even parity situation, the opposite would be true.
One such parity scheme is shown for a time division switching system employing PCM data transmission by U.S. Pat. No. 4,160,127, issued to M. F. Slana, on July 30, 1979. This patent teaches the use of a parity generation and detection process. Parity is generated before data enters a particular functional block and parity is checked after the data emerges from that functional block.
This kind of validity checking arrangement is inefficient since parity must be generated a number of times. In addition, each of the parity generating circuits is itself susceptible to faults. As a result, this configuration maximizes the chances for generating erroneous parity.
Accordingly, it is the object of the present invention to provide a data validity checking arrangement which actively transmits parity along with PCM data samples through the space switching stage of a digital switching system in an efficient manner to minimize faults.